UK HPC systems

Every UK HPC system I come across, with where it is, who runs it, what it is part of, and how big it is. I’ll keep adding to this page from time to time, so check the date it was last modified, under the title.

This first iteration has the systems that came up at the HPC-AI Advisory Council UK 2026, plus JUPITER, the EuroHPC system UK researchers can apply for. The data is a few YAML files next to this page, and everything below is drawn from them in your browser.

How big a system is, is its peak FP64, worked out from its hardware (see how). It is the one measure every system has, CPU or GPU, though it undersells an AI system, which is built for lower precision.

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How big

A tick across a bar is the system’s Rpeak on the TOP500 ( of them), for what the site measured, which can be a part of the system. Not shown, as no peak can be worked out for them yet: .

Where

A circle’s area is the system’s peak, and the small dot is where it is, hollow if it has no peak yet. Systems at the same site are spread around it.

From tiers to programmes

On the left, the tier a system was funded under in the old scheme, or “No tier” for one built since; on the right, the programme it is part of now. A system under two of either is split between them. See the summary for what the change is.

The programmes

All of them

Each system

How peak FP64 is worked out

A system’s peak is the sum over its hardware: how many of a part it has, times the part’s peak. A part’s peak is the same formula for a CPU and a GPU, with a different unit and clock:

• CPU: cores × FP64 operations per cycle per core × clock, the base clock unless the maximum boost clock is chosen above. The operations per cycle come from the core’s vector units: two 512-bit FMA units do 2 × 8 doubles × 2 = 32 per cycle (Zen 5 in AMD’s EPYC 9005, Intel’s Xeons since Skylake), and two 256-bit ones 16 (Zen 2 and 3). Zen 4 runs AVX-512 double-pumped on its 256-bit units, two cycles per instruction, so it does 16 too.
• GPU: SMs (or CUs, or Xe cores) × FP64 operations per cycle per SM × boost clock, on the matrix (tensor) units where the GPU has an FP64 rate for them, or on the vector units, as chosen above.

Where the vendor does not publish what the formula needs (NVIDIA’s B200), the vendor’s own peak is used instead. The base clock is the default because it is what the TOP500’s Rpeak uses for a CPU: ARCHER2’s 25.80 PFLOPS is exactly its measured 716,800 cores × 16 × 2.25 GHz, and Cirrus’s 4.97 PFLOPS its 70,560 cores × 32 × 2.2 GHz, which also confirms Zen 5c’s 32. The boost clock is an upper bound that no code sustains on every core. For NVIDIA’s Hopper systems, the Rpeak is about ¾ of what NVIDIA’s own 67 TFLOPS per GPU gives.